Change Log

This file lists all important changes to ATS9360 Firmware

[21.13] - 2020-11-26

• Disabled Trigger Enable flush circuit. It was causing data corruption with certain trigger rates where 64 extraneous points would be injected into the data stream.

[21.09] - 2018-11-26

• Fixed FIFO underflow problem at slow sample rates that caused DMA to stall by using fifo usage to detect overflow instead of ififo_full flag from the FIFO.

• Also added fifo_overflow bit to Reg_14[6], since Reg_14[7] does not report an overflow until after the dma finishes (this was done in v19.08 to allow users to be able to acquire data already in the on-board memory if an overflow occurred).

[21.07] - 2018-10-15

• Added protection against false triggering if trigger source is External and has a frequency higher than one trigger per record. New signal re_trigger_protection (REG58[26]) = '1' will holdoff trigger until record is done.

[21.06] - 2018-07-23

• Added logic to support data skipping with sept source lasers.

• Fixed bug in DMA logic that could have DMA'd one packet of bad data at the start of DMA.

• Uses FFT v5.2 that fixes a bug in REAL_ONLY and IMAG_ONLY outputs.

• Timeout for NPT footer now runs on a fixed 50 MHz oscillator instead of the 250 MHz LCLK that can drift over time.

[20.10] - 2017-09-01

• Added a fixed clock based timestamp for k-clock based systems. Reg_15[30] must be set to ‘1’ to use this feature.

[20.09] - 2017-04-10

• Fixed CH B datapath in NRC module.

• Every other bit was connected to GND.

• This firmware Uses FFT 4.7.

[20.06] - 2017-04-06

• Fixed bug in Trigger Module that was missing internal triggers.

• Used hyst_off_level[] instead of level[] for hyst_ok.

[20.05] - 2017-03-22

• Made changes to Post trig end pulse so it occurs earlier. This allows almost zero re-arm time. This early re-arming works only for external triggering.

[20.03] - 2016-11-28

• Interleaved NPT footer in dual channel mode so after interleaving in dual channel mode, it will look the same as in single channel.

[20.01] - 2016-08-22

• Connected AUX_INPUT to REG_02[15]. Previous firmware had this bit connected to '0', causing the Digital Input feature to not work.

[19.15] - 2016-04-26

• Disabled flushing of VFIFO at the end of Trigger Enable. This was causing data corruption problems.

[19.14] - 2016-04-21

• Used FFT core 4.5 that does fast zero-padding. Also reports dsp clk frequency, so sw can determine the max allowable trigger rate.

[19.10] - 2016-01-14

• Changed Frame Counter to not use CLK_EN. This was causing missed frame pulses if k-clock was not on when the frame start pulse occurred.

[19.09] - 2015-12-18

• Fixed NPT Pretrigger bug where the first record was not being captured properly if NPT pre-trigger was selected (slow ext clock en polarity was reversed).

[19.08] - 2015-12-02

• Increased VFIFO depth to 29. Previous depth was 27 which overflowed at 2GB instead of 8GB.

• Also implemented VFIFO protection mode that will not tell software VFIFO overflowed until all data has been DMA’d out of VFIFO.

[19.07] - 2015-11-17

• Increased NPT record length counter to be 2^28 instead of 2^24 in previous versions.